All-digital phase-lock-loops (ADPLLs) are widely used in advanced CMOS technology. ADPLLs typically include high resolution time-to-digital converters (TDC) and LC-based digitally controlled oscillators (LC-DCO). Such configuration reduces area consumption and power dissipation in the ADPLL. The ADPLL also typically includes a digital loop filter, a reference clock accumulator, a variable clock accumulator and a feedback divider.
Compared to analog phase lock loops, an ADPLL with an LC-DCO exhibits lower phase noise with lower power consumption and lower frequency pushing (i.e., smaller output frequency variations due to supply voltage variation and/or noise). In addition, the LC-DCO is generally immune from process and temperature variations. The ADPLL with an LC-DCO, however, has a relatively smaller tuning range and occupies a relatively large space on the chip when compared to analog PLLs, for example.
Magnetic coupling techniques can be used for increasing the tuning range without extra area consumption by an LC-DCO by decreasing the inductance of an inductor or transformer-based LC tank of the LC-DCO. Implementations with a single-turn and fixed switches, however, provide a limited tuning range extension. Additionally, such magnetic coupling techniques decrease the total quality factor of the LC tank of the LC DCO due to a switch resistor coupling effect.